Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. It is generally desirable that ICs operate as fast as possible, and consume as little power as possible. There is also a continuing effort to reduce the size of devices in ICs to result in more chips per substrate, and/or with greater functionality. However, as device sizes shrink, certain parasitic effects increase.
One problem that arises in metal-oxide-semiconductor (“MOS”) transistors, which are commonly used in ICs, is internal leakage between the source and the drain. Internal current leakage is one of the limiting factors in reducing device size. As the source becomes closer to the drain (i.e., as the channel length of a MOS transistor is reduced), the drain potential is more likely to couple into the channel, which results in drain-induced barrier lowering (“DIBL”). DIBL can result in failure of a transistor having a short channel length.
Another problem involves current leakage from the source and drain to the substrate. Although the source typically forms a reversed-biased PN junction with the substrate, as the physical dimensions decrease the PN junction current increases. The parasitic capacitances of the source and drain with the substrate also become increasingly important.
One approach to reducing current leakage has been to use a semiconductor-on-insulator (“SOI”) substrate, which generally surrounds each active device with insulating material(s). However, in SOI approaches the body of a device floats, creating an ambiguous voltage between the source/drain and the body that depends on the biasing history and recombination mechanisms of the device. This undesirable effect is referred to as the “floating body effect.”
It is desirable to provide a MOS device having reduced channel leakage and parasitic capacitance, while avoiding the floating body effect.